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92910 sy no.1812-1/20 LE24CBP222 overview the power switch integrated triple po rt eeprom series consists of two independent banks, and each bank can be controlled separately using dedicated control pins. the eeprom also features a control port, which is a third pin separate from the pins used for the ba nks, and by accessing the memory areas from this control port, the two-bank configuration (2k bits + 2k bits) can be used as a pseudo-one-bank configuration (4k bits). together with the 16-byte page write function, this enables a reduction in the number of fact ory write processes. furthermore, the eeprom has a configuration area which is separate from the 2k-bit + 2k -bit area, and by using the settings stored in this configuration area, it is possible to change the slave address for each port and to set read/write protection for each port. the eeprom also incorporates a power switch circuit with reverse current blocking diodes, supporting different power voltages among three ports. this product incorporates sanyo's high performance cmos eeprom technology and realizes high-speed operation and high-level reliability. the interface of th is product is compatible with the i 2 c bus protocol, making it ideal as a nonvolatile memory for small-scale parameter storage. in addition, this product also supports ddc2 tm , so it can also be used as an edid data storage memory for display equipment. functions ? capacity : bank1:2k bits (256 8 bits) + bank2:2k bits (256 8 bits) + configuration area: 128 bits (16 8 bits), 4224 bits in total ? single supply voltage : 2.7v to 5.5v . with built-in power switch circuit. ? interface : two wire serial interface (i 2 c bus * ), vesa ddc2 tm compliant ** 3-port access ? operating clock frequency : 400khz (max) ? low power consumption : standby: 40 a (max), one-bank read: 8 ma (max.) continued on next page. ordering number : en*a1812 cmos ic power switch integrated triple port eeprom two wire serial interface (2k+2k eeprom) * : i 2 c bus is a trademark of philips corporation. ** : ddc and edid are trademarks of video electronics standard association (vesa). * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LE24CBP222 no.1812-2/20 continued from preceding page. ? automatic page write mode: 16 bytes ? slave address setting : slave ad dress can be set for each port. ? protect function : read/write pr otection can be set for each port. ? read mode : sequential read and random read ? erase/write cycles : 10 6 cycles ? data retention : 20 years ? high reliability : adopts sanyo?s proprietary sy mmetric memory array configuration (usp6947325) noise filters connected to scl1/sda 1, scl2/sda2 and sclc/sdac pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : LE24CBP222m mfp10s (225mil) package dimensions unit:mm (typ) 3086b [le24cbk222m] pin assignment pin descriptions pin.1 scl1 clock input pin.2 sda1 data input/output pin.3 v dd 1 power supply port 1 pin.4 sda2 data in put/output port 2 pin.5 gnd ground pin.6 sdac data input/output pin.7 sclc clock input pin.8 v dd c power supply control port pin.9 scl2 clock input pin.10 v dd 2 power supply port 2 sanyo : mfp10s(225mil) 1 10 5 6 (0.5) 1.7max 1.0 0.35 5.0 0.15 6.4 (1.5) 0.1 4.4 0.63 scl1 sda1 sda2 gnd scl2 sclc sdac 1 2 3 4 5 6 7 8 9 10 v dd 1 v dd 2 v dd c
LE24CBP222 no.1812-3/20 block diagram description of operation access to bank1 is performe d through port 1 (scl1 / sda1), and access to bank2 through port 2 (scl2 / sda2). when read operations are performed, bank1 and bank2 can be controlled independently of each other and both banks can be accessed at the same time. when write operations ar e performed, it is not possible to access both banks while a write operation is in progress in one of the banks (including the write wait time). both bank1 and bank2 can be accessed from the control port (sclc, sdac). the two-bank configuration (2k bits + 2k bits) can be used as a pseudo-one-bank configuration (4k bits). data correlation is guaranteed between the mode in which accesses are made from port1 or port 2 and the mode in which accesses are made from the control port, enabling operations such as writing data from control port in a lump and reading data from port 1 or port 2. access to the configuration area where the slave addresses of the ports and protect information is stored is made from the control port. if a voltage of a different level is supplied from the ports, the built-in power switch ci rcuit prevents reverse flow of current between power supplies, providing a stable power voltage into the ic. specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +6.5 v dc input voltage -0.5 to +5.5 v over-shoot voltage below 20ns -1.0 to +6.5 v storage temperature tstg -65 to +150 c * vdd denotes the supply voltage of the port pin. the maximum pin voltage must not exceed 6.5v. operating conditions parameter symbol conditions ratings unit operating supply voltage 2.7 to 5.5 v operating temperature -40 to +85 c port 1 sda1 scl1 port 2 sda2 scl2 port control port control bank1 (2k eeprom) bank2 (2k eeprom) port control state control control port sdac sclc configuration area protect info. slave address slave enable v dd 1 v dd 2 level shifter level shifter level shifter v dd c internal v dd v dd 1 v dd 2 v dd c power switch
LE24CBP222 no.1812-4/20 dc electrical characteristics parameter symbol conditions typ. min. max unit supply current at reading (when either one-bank is read) i cc 11 f=400khz 8 ma supply current at reading (when both two-bank are read simultaneously) i cc 12 f=400khz 8 ma supply current at writing i cc 2 f=400khz, t wc =5ms 5 ma port1 standby current i sb 1 v in =v dd 1 or gnd 0.7 40 a port2 standby current i sb 2 v in =v dd 2 or gnd 0.7 40 a control port standby current i sb c v in =v dd c or gnd 0.7 40 a port1 input leakage current i li 1 v in =gnd to v dd 1 -2.0 +2.0 a port2 input leakage current i li 2 v in =gnd to v dd 2 -2.0 +2.0 a control port input leakage current i li c v in =gnd to v dd c -2.0 +2.0 a port1 output leakage current i lo 1 v out =gnd to v dd 1 -2.0 +2.0 a port2 output leakage current i lo2 1 v out =gnd to v dd 2 -2.0 +2.0 a control port output leakage current i lo c v out =gnd to v dd c -2.0 +2.0 a port1 input low voltage v il 1 v dd 1*0.3 v port2 input low voltage v il 2 v dd 2*0.3 v control port input low voltage v il c v dd c*0.3 v port1 input high voltage v ih 1 v dd 1*0.7 v port2 input high voltage v ih 2 v dd 2*0.7 v control port input high voltage v ih c v dd c*0.7 v i ol =0.7ma, v dd 1=2.7v 0.2 v i ol =3.0ma, v dd 1=2.7v 0.4 v i ol =3.0ma, v dd 1=5.5v 0.4 v port1 output low level voltage v ol 1 i ol =6.0ma, v dd 1=4.5v 0.6 v i ol =0.7ma, v dd 2=2.7v 0.2 v i ol =3.0ma, v dd 2=2.7v 0.4 v i ol =3.0ma, v dd 2=5.5v 0.4 v port2 output low level voltage v ol 2 i ol =6.0ma, v dd 2=4.5v 0.6 v i ol =0.7ma, v dd c=2.7v 0.2 v i ol =3.0ma, v dd c=2.7v 0.4 v i ol =3.0ma, v dd c=5.5v 0.4 v control port output low level voltage v ol c i ol =6.0ma, v dd c=4.5v 0.6 v capacitance /ta=25 c, f=100khz parameter symbol conditions min typ max unit in/output capacitance c i/o v i/o =0v (sda1, sda2, sdac) 2 5 pf input capacitance c i v in =0v (scl1, scl2, sclc) 2 5 pf note: this parameter is sampled and not 100% tested.
LE24CBP222 no.1812-5/20 ac electric characteristics fast mode v dd =2.7v to 5.5v parameter symbol min typ max unit slave mode scl clock frequency f scls 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl, sda rise time t r 300 ns scl, sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms standard mode v dd =2.7v to 5.5v parameter symbol min typ max unit slave mode scl clock frequency f scls 100 khz scl clock low time t low 4700 ns scl clock high time t high 4000 ns sda output delay time t aa 100 3500 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 4700 ns start condition hold time t hd.sta 4000 ns data in setup time t su.dat 250 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 4000 ns scl, sda rise time t r 1000 ns scl, sda fall time t f 300 ns bus release time t buf 4700 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms
LE24CBP222 no.1812-6/20 bus timing write timing pin functions (port1: for bank1) scl1 (serial clock input) pin the scl1 pin is the serial clock input pin used to access the bank1 area, and pro cesses signals at th e rising and falling edges of the scl1 clock signal. this pin must be pulled up by a resistor to the v dd 1 level, and wired-ored with another open drain (or open collector) output device for use. while this product is being accessed from the control port, it cannot be accessed from port 1. sda1 (serial data input/output) pin the sda1 pin is used to transfer serial data to the input/output of the bank1 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl1 line, the sda1 line must be pulled up by a resistor to the v dd 1 level and wired-ored with another open drai n (or open collector) ou tput device for use. while this product is being accessed from the control port, it cannot be accessed from port 1. (port2: for bank2) scl2 (serial clock input) pin the scl2 pin is the serial clock input pin used to access the bank2 area, and pro cesses signals at th e rising and falling edges of the scl2 clock signal. this pin must be pulled up by a resistor to the v dd 2 level, and wired-ored with another open drain (or open collector) output device for use. while this product is being accessed from the control port, it cannot be accessed from port 2. sda2 (serial data input/output) pin the sda2 pin is used to transfer serial data to the input/output of the bank2 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl2 line, the sda2 line must be pulled up by a resistor to the v dd 2 level and wired-ored with another open drai n (or open collector) ou tput device for use. while this product is being accessed from the control port, it cannot be accessed from port 2. (control port: for accessing both banks a nd for accessing the configuration area) sclc (serial clock input) pin the sclc pin is the serial clock input pin used for acce ssing both the bank1 and bank2 areas and the configuration area. the signals are processed at the rising and falling edges of the sclc clock signal. the pin must be pulled up by a resistor to the v dd c level, and it is wired-ored with another open drain (or open collector) output device for use. sdac (serial data input/output) pin the sdac pin is used to transfer serial data to the input/output of both bank1 and bank2 areas and the configuration area, and it consists of a signal input pin and n-channel transistor open drain output pin. like the sclc line, the sdac line must be pulled up by a resistor to the v dd c level, and it is wired-ored with another open drain (or open collector) output device for use. scl sda d0 t wc write data acknowledge stop condition start condition scl sda/in sda/out t f t su.sta t hd.sta t aa t high t low t hd.dat t hd.sta t dh t r t su.sto t sp t buf t sp
LE24CBP222 no.1812-7/20 functional description 1. start condition when the scl line is at the high level, the start condition is established by changing the sda line from high to low. the operation of the eeprom as a slave starts in the start condition. 2. stop condition when the scl line is at the high level, the stop condition is established by changing the sda line from low to high. when the device is set up for the read sequence, the read operation is suspended when th e stop condition is received, and the device is set to standby mode. when it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the eeprom internal write operation is started. 3. data transfer data is transferred by changing the sd a line while the scl line is low. when the sda line is changed while the scl line is high, the resulting condition will be recognized as the start or stop condition. 4. acknowledge during data transfer, 8 bits are transf erred in succession, and then in the nint h clock cycle period the device on the system bus receiving the data sets the sda line to low, and sends the acknowledge signal indicating that the data has been received. the ackn owledge signal is not sent during an eeprom internal write operation. scl sda t su.sta t hd.sta t su.sto start condition stop condition t aa t dh 1 89 scl (eeprom input) sda (master output) sda (eeprom output) start condition acknowledge bit output scl sda t su.dat t hd.dat
LE24CBP222 no.1812-8/20 5. device addressing for the purposes of communication, the master device in the system generates the start condition for the slave device. communication with a particular slave device is enabled by sending along the sda bus the device address, which is 7 bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. the upper four bits of the device address are called the de vice code which, for this product, are fixed at ?1010b.? the 3-bit slave address (sa2, sa1, an d sa0 for access from port 1; sb2, sb1, and sb0 for access from port 2; sc2 and sc1for access from the control port) following the de vice code are stored in the configuration area, and any values can be set for these addresses. however, the device address to be used to access the configuration area is fixed at ?1011_100b? and cannot be changed. when the device code input from sda and the slave addr esses are compared with the product?s device code and configuration area that were set at the mounting stage an d found to match, the product sends the acknowledge signal during the ninth clock cycle period, and initiates the read or write opera tion in accordance with the read or write command code. if they do not match, the eeprom returns to standby mode. when a read operation is performed immediately after the slave device has been switched, the random read command must be used. the slave addresses are set as follows when this product is shipped. (sa2, sa1, sa0) = (0, 0, 0) (sb2, sb1, sb0) = (0, 0, 0) (sc2, sc1) = (0, 0) 1 00 1 sa2 sa1 sa0 r/w msb lsb 1 00 1 sb2 sb1 sb0 r/w msb lsb 1 00 1 sc2 sc1 a8* r/w msb lsb 1 01 1 r/w msb lsb 1 0 0 port 1 port 2 device code slave address device address word control port (when you access bank1, bank2) control port (when you access configuration area) *a8=0:bank1 access a8=1:bank2 access
LE24CBP222 no.1812-9/20 6 internal mode this product functions in bank mode when it is accessed from port 1 or port 2 and in combined mode when it is accessed from the control port. 6-1. bank mode the eepom functions in the bank mode when it is accessed from port 1 or port 2. in the bank mode, bank1 is controlled from the port 1 pins (scl1, sda1), and bank2 is controlled from the port 2 pins (scl2, sda2). when read operations are performed, the two banks can be controlled independently of each other, and access to different addresses can be made at the same time. this enables the eeprom to be handled as two independent eeprom devices incorporated in a single package. in turn, this makes it possible for the bank1 and bank2 sides to be connected to the mcu of separate systems. when write operations are performed, it is not possible to wr ite data in two banks at the same time. after the write data has been input into one of the banks and the internal rewriting operation has started, access to the two banks is not possible during the write time twc period. 6-2. combine mode the eeprom functions in the combined mode when it is accessed from the control port. in the combined mode, bank1 and bank2 are controlled from the control port pins (sclc, sdac). the combined mode uses the two-bank configuration (2k bits + 2k bits) as a pseudo-one-bank configuration (4k bits). since the memory area is processed as a single 4k-bit bank in this mode, the msb address changes from a7 to a8. input a8=0 to control the bank1 area, and input a8=1 to co ntrol the bank2 area. when, in the combined mode, the last ad dress (0ffh) of bank1 has been reached in a sequential read operation, the address (100h) in the bank2 side is sequentially read. similarly, when the last address (1ffh) of bank2 has been reached, it is rolled over to the ba nk1 address (000h) and continues to be read into this address. data correlation is guaranteed between the bank mode an d combined mode, enabling operations while switching the mode such as performing write in the combined mode and read in the bank mode. while the eeprom is functioning in the combined mode, acce ss from port 1 and port 2 is disabled. in the bank mode, the read operation stops while data is being read from the ports. and, in the bank mode, while the data of one of the banks is being written, access from the control port is disabled until th e internal write operation is completed. scl1 sda1 scl2 sda2 LE24CBP222 00h ffh bank1 (2k-bit) 00h ffh bank2 (2k-bit) sclc sdac scl2 sda2 LE24CBP222 000h 0ffh bank1 (2k-bit) 100h 1ffh bank2 (2k-bit) scl1 sda1
LE24CBP222 no.1812-10/20 fig.: configuration area memory map address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0h slv_enbc sc2 sc1 1h slv_enb1 sa2 sa1 sa0 2h slv_enb2 sb2 sb1 sb0 3h reserved r/w 4h reserved r/w 5h reserved r/w 6h reserved r/w 7h reserved r/w 8h pb1c pb0c 9h pb1a pb0a ah pb1b pb0b bh reserved r/w ch reserved r/w dh reserved r/w eh reserved r/w fh device revision (reserved r only) 7. configuration area it can access the configuration area. this product has a configur ation area equivalent to 16 addresses that is separate from bank1 and bank2. refer to the above table for th e memory map of the configuration area. access to the configuration area is performed by inputting de vice address ?1011_100b? from the control port. 7-1. slave address bits (sa2, sa1, sa0, sb2, sb1, sb0, sc2, sc1) the slave address bits are used to set the slave address in the device address. this product does not have slave address pins, but has slave address bits inside instead. by ch anging the values of these bits, it is possible to change the slave addresses at any time. each port contains a slave address bit, and a different slave address can be assigned to the ports. port slave address bit port 1 sa2, sa1, sa0 port 2 sb2, sb1, sb0 control port sc2, sc1 7-2. slave address enable bits (slv_enb1, slv_enb2, slv_enbc) the slave address enable bits (slv_enb) are used to enable or disable the slave addresses of the ports, which have been set in the configuration area. when slv_enb=?0,? the slave address bits of the ports which have been set in the configuration area are disabled, and the slave address value input in the device address is don?t care. when another slave device exists on the same bus as the eeprom, slv_enb=?1? must be set without fail. port slave address enable bit port 1 slv_enb1 port 2 slv_enb2 control port slv_enbc 7-3. protect bits (pb1a, pb0a, pb1b, pb0b, pb1c, pb0c) the protect bits are used to set the access level. the value of the protect bits determine wh ether the product is to be protected against read and write operations. the protect bits can be set for each port. pb1n pb0n access level 0 0 access inhibit 0 1 read write prohibition. only the acknowledge response. 1 0 write prohibition. only the read. 1 1 read write possible. 7-4. reserved r/w the bits in addresses 3h to 7h and bh to eh in the conf iguration area are reserved bits, and have no significance. read and write are possible in the areas with these addresses, but it is re commended that the areas not be used. 7-5. device revision the revision code of this product is stored in the fh address of the configuration area. it is read-only and cannot be rewritten with a write operation.
LE24CBP222 no.1812-11/20 8 eeprom write operation 8-1. byte writing when the eeprom receives the 7-bit device address an d write command code ?0? after the start condition, it generates an acknowledge signal. after this, if it receives the 8-bit word addr ess, generates an acknowledge signal, receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write operation of the eeprom in the designated memory ad dress will start. rewriting is completed in the t wc period after the stop condition. during an eeprom internal write oper ation, no input is accepted and no acknowledge signals are generated. 8-2. page writing this product enables pages with up to 16 bytes to be written. the basic data transfer procedure is the same as for byte writing: following the start condition, the 7-bit device addr ess and write command code ?0,? word address (n), and data (n) are input in this order while confirming acknowledge ?0? every 9 bits. the page write mode is established if, after data (n) is input, the write data (n+1) is input w ithout inputting the stop condition. after this, the write data equivalent to the largest page size can be received by a continuous process of repeatin g the receiving of the 8-bit write data and generating the acknowledge signals. at the point when the write data (n+1) has been input, the lower 4 bits (a0-a3) of the word addresses are automatically incremented to form the (n +1) address. in this way, the write data can be successively input, and the word address on the page is incremente d each time the write data is input. if th e write data exceeds 16 bytes or the last address of the page is exceeded, the word address on the page is rolled over. write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. finally, the eeprom internal write operation corresp onding to the page size for which the wr ite data is received starts from the designated memory address when the stop condition is received. sda a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start word address data s2, s1, s0 : slave address a8 : bank selecting address used during control port sccess access from master sda a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start memory address(n) data(n) d7 d6 d1 d0 ack d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 stop ack ack ack data(n+1) data(n+x) s2, s1, s0 : slave address a8 : bank selecting address used during control port sccess access from master
LE24CBP222 no.1812-12/20 8-3. acknowledge polling acknowledge polling is used to find out when the eeprom internal write operation is completed. when the stop condition is received and the eeprom starts rewriting, all opera tions are prohibited, and no response can be given to the signals sent by the master device. therefore, in orde r to find out when the eeprom internal write operation is completed, the start condition, device address and write command code are sent from the master device to the eeprom (slave device), and the respon se of the slave device is detected. in other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. sda no ack r/w w s0 / a8 s1 s2 0 1 0 1 start w s0 / a8 s1 s2 0 1 0 1 start w s0 / a8 s1 s2 0 1 0 1 start no ack r/w ack r/w s2, s1, s0 : slave address a8 : bank selecting address used during control port access access from master during write during write end of write
LE24CBP222 no.1812-13/20 9 eeprom read operations 9-1. current address reading the address equivalent to the memory address accessed last +1 is held as the internal address of the eeprom for both write* and read operations. theref ore, provided that the master device has recognized the position of the eeprom address pointer, data can be read from the memory address with the current address pointer without specifying the word address. as with writing, current address read ing involves receiving the 7-bit device address and read command code ?1? following the start condition, at which time the eeprom gene rates an acknowledge signal. after this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. after the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the eeprom completes the read operation and is set to standby mode. if the previous read address is the last address, the address for the current address reading is rolled over to become address 0. * the current address assigned after a pa ge write is the number of bytes written at the designated word address plus 1 if the volume of the write data is greater than 1 byte or le ss than or equal to 16 bytes, and is the designated word address if the volume of the write data is 16 bytes or more. if the last address of the page (a3 to a0 = 1111b) is specified as the word address for a byte write, the internal addr ess after the write becomes the first address in that page (a3 to a0 = 0000b). 9-2. random read random read is a mode in which any memory address is sp ecified and its data read. the address is specified by a dummy write input. first, when the eeprom receives the 7-bit device address and write command code ?0? following the start condition, it generates an acknowledge signal. it then receives the 8-bit word address, and generates an acknowledge signal. through these operations, the word address is load ed into the address count er inside the eeprom. next, the start condition is input again and the current read is initiated. this causes the data of the word address that was input using the dummy write input to be output. if, after the data is output, an acknowledge signal is not sent and the stop condition is input, reading is completed, and the eeprom returns to standby mode. sda a7 a6 a5 a4 a3 a2 a1 a0 no ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start device address word address d7 d0 stop data(n) r s0 / a8 s1 s2 0 1 0 1 start device address ack r/w dummy write current address read s2, s1, s0 : slave address a8 : bank selecting address used during control port access access from master sda d7 d6 d5 d4 d3 d2 d1 d0 no ack ack r/w r s0 / a8 s1 s2 0 1 0 1 start device address stop s2, s1, s0 : slave address a8 : bank selecting address used during control port access access from master data(n+1 address)
LE24CBP222 no.1812-14/20 9-3. sequential read in this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. if, after the 8-bit data has been output, acknowledge ?0? is input and reading is continued without issuing the stop condition, the address is increm ented, and the data of the next address is output. if acknowledge ?0? continues to be input after the data has been output in this way, the data is successively output while the address is incremented. when the last address is reached, it is roll ed over to address 0, and the data continues to be read. as with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. *: for accesses from port 1 or po rt 2, the last address is ffh and for accesse s to bank1 or bank2 from the control port, it is 1ffh. and, for accesses to the configuration area, the last address is fh. 10. operations during protect the access level can be set for each port by using the values of the protect bits stored in the configuration area. however, access to the config uration area from the control port (dev ice address 1011_100b) is always enabled regardless of the access level of the control port. 10-1. access disabled st ate (pb1n=0, pb0n=0) when the protect bits in the configuration area are set to?0 0b,? all the operations from the corresponding port are protected, and the access from the port is di sabled. when a read or write operation is input from a port in this state, the product does not start the operation and enters the standby state. in addition, it does not return an acknowledge signal. 10-2. read/write disabled state (pb1n=0, pb0n=1) when the protect bits in the configuration area are set to ?0 1b,? the read and write operat ions from the corresponding port are protected. when a read or wr ite operation is input from a port in this state, the product returns an acknowledge signal and enters the standby state w ithout initiating a read or write operation. *: in read operations, the product generates an acknowledge signal on the high-to-low transition of the scl clock in the 9 th cycle from the start condition. it enters the standby state on the low-to-high transition of the scl clock in the same cycle. 10-3. write prohibited state (pb1n=1, pb0n=0) when the protect bits in the configuration area are set to ?10b,? the write operations from the corresponding port are protected. when a write operation is input from a port in this state, the product returns an acknowledge signal and enters the standby state without initiating a write operation. 10-4. read/write enabled state (pb1n=1, pb0n=1) when the protect bits in the configuration area are set to ?11b,? the read operations and write operations from the corresponding port are enabled. sda ack r/w r s0 / a8 s1 s2 0 1 0 1 start stop no ack device address data(n) data(n+1) d7 d6 d1 d0 d7 d6 d1 d0 ack ack d7 d6 d1 d0 data(n+x) s2, s1, s0 : slave address a8 : bank selecting address used during control port access access from master
LE24CBP222 no.1812-15/20 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l example: when v dd =3.0v and i l = 2 a r pu maximum value = (3.0v ? 3.0v 0.8)/2 a = 300k r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of sanyo?s eeprom must be set. r pu minimum value = (v dd ? v ol )/i ol example: when v dd =3.0v, v ol = 0.4v and i ol = 1ma r pu minimum value = (3.0v ? 0.4)/1ma = 2.6k recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k . scl sda 1 2 89 dummy clock 9 start condition start condition sda r pu c bus i l eeprom i l master device
LE24CBP222 no.1812-16/20 3) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. item symbol min typ max unit power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instruction 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. b. if it is not possible to satisfy the instruction 2 in note above after the power has stabilized, soft ware reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) power switch circuit this product incorporates a power switch circuit that controls the power supplied to the ports. it prevents reverse flow of current between power supplies. the circuit also monitors the power status of the ports. the power voltage to the port to be accessed must always be in operating range of between 2.7v and 5.5v. 5) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 6) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. v dd 0v t off t rise v bot t low t dh t su.dat v dd scl sda t su.dat v dd scl sda
LE24CBP222 no.1812-17/20 7) initial values in the configuration the slave address values as well as the slave address enable bit and protect bit values of the ports are stored in the configuration area. these values are set as follows when the eeprom is shipped: - slave address values: ?000b? for all ports - slave address enable bits: ?1b? for all ports (enabled) - protect bit values: ?11b? for all ports (no protection) when these values are to be changed, input the device address ?1011_100b? from the co ntrol port, and perform the write operation. 8) precautions when changing the mode this product enables to actively change the bank accessing mode during period in which no write operation is performed between the bank operation mode (access from port 1 or port 2 to bank1 or bank2) and the combined operation mode (access from the control port to both banks). however, the current address value for each mode is not held internally. when conducting read operations after ch anging the mode, random access read must be performed without fail. when switching the bank accessing mode, start the operations in the next mode after the operations in the previous mode have been completed (when the stop condition is in put or no acknowledge ?0? input for a sequential read). 9) batch writing from the control port this product enables two-bank configuration (2k bits + 2k bits) to be used as a pseudo-one-bank configuration (4k bits) by accessing the memory areas from the control port (sclc, sdac). as a result, data can be batch written with the eeprom serving as a regular 4k-bit eeprom. fix the port 1 and port 2 pins to high or low. memory area (4k-bit) the msb address in combined mode is a8. a8 is used to select the bank1 or bank2 area. set a8 = 0 to control the bank1 area, or a8 = 1 to control the bank2 area. bank1 (2k-bit) bank2 (2k-bit) 000h 0ffh 100h 1ffh a8=0 a8=1
LE24CBP222 no.1812-18/20 10) system configuration image (hdmi system) this product can support two hdmi po rts simultaneously. both ports can be accessed at the same time when performing read operations of the ports. all the data can be written together from a image processor into the areas allocated to the two ports from the control port in a single operation. lcd-tv i 2 c LE24CBP222 port 1 port 2 control port hdmi switch tmds tmds ddc ddc level shifter level shifter hdmi connector hdmi connector hdmi receiver image processor
LE24CBP222 no.1812-19/20 10) peripheral circuit diagram example of connection with hdmi receiver the le25cbp222 incorporates a reverse current preventing function which allows 3v and 5v power supplies to be connected directly to the ic with no external diodes. *1: system power supply (3v) for hdmi receiver, etc. *2: level shifter when connecting the 5v hdmi connector side with a 3v syst em, level shifters must generally be inserted. however, this is not necessary when the hdmi receiver supports 5v input signals. *3: pull-up resistors for the i 2 c and ddc interfaces. see item 2) in the application notes for the resistance value settings. ddc+5v ddc_clk ddc_dat gnd ddc+5v ddc_clk ddc_dat gnd 1:scl1 LE24CBP222 2:sda1 9:scl2 4:sda2 5:gnd 7:sclc 6:sdac 3:v dd 1 hdmi switch scl1 sda1 scl2 sda2 *2 (level shifter) hdmi recever scl(3v) sda(3v) v dd (3v) *3 r pu controller v dd (3v) v dd (3v)*1 *3 r pu *3 r pu 10:v dd 1 8:v dd c *3 r pu hdmi connector hdmi connector
LE24CBP222 no.1812-20/20 ps this catalog provides information as of september, 2010. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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